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SV/Verilog Testbench
SV/Verilog Design
Results
[2013-07-27 23:54:03 UTC] cver design testbench
GPLCVER_2.12a of 05/16/07 (Linux-elf).
Copyright (c) 1991-2007 Pragmatic C Software Corp.
All Rights reserved. Licensed under the GNU General Public License (GPL).
See the 'COPYING' file for details. NO WARRANTY provided.
Today is Sat Jul 27 23:54:03 2013.
Compiling source file "design"
Compiling source file "testbench"
Highest level modules:
test

Read initial data.
data[1b]: x
Write new data.
Read new data.
data[1b]: c5
1 simulation events and 22 declarative immediate assigns processed.
37 behavioral statements executed (12 procedural suspends).
Times (in sec.): Translate 0.0, load/optimize 0.1, simulation 0.1.
There were 0 error(s), 0 warning(s), and 7 inform(s).
End of GPLCVER_2.12a at Sat Jul 27 23:54:03 2013 (elapsed 0.0 seconds).
Done

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