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SV/Verilog Testbench
SV/Verilog Design
Results
[2013-07-28 22:11:43 UTC] veriwell design testbench


Veriwell version 2.8.7,
Copyright (C) 1993-2008 Elliot Mednick and Mark Hummel

Veriwell comes with ABSOLUTELY NO WARRANTY; This is free
software, and you are welcome to redistribute it under the
terms of the GNU General Public License as published by
the Free Software Foundation; either version 2 of the License,
or (at your option) any later version.

lxt support compiled in
lxt2 support compiled in

Entering Phase I...
Compiling source file : design
Compiling source file : testbench

Entering Phase II...
Entering Phase III...
No errors in compilation
Top-level modules:
test

Read initial data.
data[1b]: x
Write new data.
Read new data.
data[1b]: c5
0 Errors, 0 Warnings, Compile time = 0.0, Load time = 0.0, Simulation time = 0.0

Normal exit
Thank you for using Veriwell
Done

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