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SV/Verilog Testbench
SV/Verilog Design
Results
[2013-11-14 13:04:19 UTC] iverilog '-Wall' '-DNO_GATES' design testbench && unbuffer vvp a.out
VCD info: dumpfile dump.vcd opened for output.
Finding VCD file...
./dump.vcd
[2013-11-14 13:04:19 UTC] Opening EPWave...
Done

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