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SV/Verilog Testbench
SV/Verilog Design
Results
[2014-08-09 17:56:51 EDT] vlib work && vlog '-timescale' '1ns/1ns' '-sv2k9' +incdir+$UVM_HOME/src -l uvm_1_2 -err VCP2947 W9 -err VCP2974 W9 -err VCP3003 W9 -err VCP5417 W9 -err VCP6120 W9 -err VCP7862 W9 -err VCP9201 W9 -err VCP2129 W9 design.sv testbench.sv && vsim -c -do "vsim +UVM_VERBOSITY=UVM_HIGH +access+r; run -all; exit"
VSIMSA: Configuration file changed: `/home/runner/library.cfg'
ALIB: Library `work' attached.
work = /home/runner/work/work.lib
MESSAGE "Pass 1. Scanning modules hierarchy."
MESSAGE_SP VCP2124 "Package uvm_pkg found in library uvm_1_2."
MESSAGE_SP VCP2124 "Package std found in library uvm_1_2."
WARNING VCP2127 "Unable to map port type: unknown for port: uvm_dpi_regcomp in library module: uvm_pkg. Connection rules will not be checked for such port." 938 4
MESSAGE "Pass 2. Processing instantiations."
WARNING VCP2597 "Some unconnected ports remain at instance: dut. Module ADD_SUB has unconnected port(s) : a0, b0, doAdd0, result0." "testbench.sv" 49 1
MESSAGE "Pass 3. Processing behavioral statements."
WARNING VCP5228 "Input port a<wire> is used as lvalue." "design.sv" 33 16
WARNING VCP5228 "Input port b<wire> is used as lvalue." "design.sv" 34 16
WARNING VCP5228 "Input port doAdd<wire> is used as lvalue." "design.sv" 35 20
MESSAGE "Running Optimizer."
MESSAGE "ELB/DAG code generating."
MESSAGE "Unit top modules: top."
MESSAGE "$root top modules: top."
SUCCESS "Compile success 0 Errors 5 Warnings Analysis time: 5[s]."
ALOG: Warning: The source is compiled without the -dbg switch. Line breakpoints and assertion debug will not be available.
done
# Aldec, Inc. Riviera-PRO version 2014.06.88.5387 built for Linux64 on June 25, 2014.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2014 Aldec, Inc. All rights reserved.
vsim +UVM_VERBOSITY=UVM_HIGH +access+r;
# ELBREAD: Elaboration process.
# ELBREAD: Warning: Package 'uvm_pkg' does not have a `timescale directive, but previous modules do.
# ELBREAD: Warning: Package 'std' does not have a `timescale directive, but previous modules do.
# ELBREAD: Elaboration time 0.7 [s].
# KERNEL: Main thread initiated.
# KERNEL: Kernel process initialization phase.
# KERNEL: Time resolution set to 1ns.
# ELAB2: Elaboration final pass...
# KERNEL: PLI/VHPI kernel's engine initialization done.
# PLI: Loading library '/usr/share/riviera-pro-2014.06-x86_64/bin/libsystf.so'
# KERNEL: Info: Loading library: /usr/share/riviera-pro-2014.06-x86_64/bin/uvm_1_2_dpi
# ELAB2: Create instances ...
# ELAB2: Create instances complete.
# SLP: Started
# SLP: Elaboration phase ...
# SLP: Elaboration phase ... done : 0.1 [s]
# SLP: Generation phase ...
# SLP: Generation phase ... done : 0.1 [s]
# SLP: Finished : 0.2 [s]
# SLP: 0 primitives and 6 (85.71%) other processes in SLP
# SLP: 5 (0.01%) signals in SLP and 18 (0.04%) interface signals
# ELAB2: Elaboration final pass complete - time: 3.8 [s].
# KERNEL: SLP loading done - time: 0.0 [s].
# KERNEL: Warning: You are using the Riviera-PRO EDU Edition. The performance of simulation is reduced.
# KERNEL: Warning: Contact Aldec for available upgrade options - sales@aldec.com.
# KERNEL: SLP simulation initialization done - time: 0.0 [s].
# KERNEL: Kernel process initialization done.
# Allocation: Simulator allocated 76112 kB (elbread=38271 elab2=32450 kernel=5390 sdf=0)
# KERNEL: UVM_INFO /home/build/vlib1/vlib/uvm-1.2/src/base/uvm_root.svh(392) @ 0: reporter [UVM/RELNOTES]
# KERNEL: ----------------------------------------------------------------
# KERNEL: UVM-1.2
# KERNEL: (C) 2007-2014 Mentor Graphics Corporation
# KERNEL: (C) 2007-2014 Cadence Design Systems, Inc.
# KERNEL: (C) 2006-2014 Synopsys, Inc.
# KERNEL: (C) 2011-2013 Cypress Semiconductor Corp.
# KERNEL: (C) 2013-2014 NVIDIA Corporation
# KERNEL: ----------------------------------------------------------------
# KERNEL:
# KERNEL: *********** IMPORTANT RELEASE NOTES ************
# KERNEL:
# KERNEL: You are using a version of the UVM library that has been compiled
# KERNEL: with `UVM_NO_DEPRECATED undefined.
# KERNEL: See http://www.eda.org/svdb/view.php?id=3313 for more details.
# KERNEL:
# KERNEL: You are using a version of the UVM library that has been compiled
# KERNEL: with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
# KERNEL: See http://www.eda.org/svdb/view.php?id=3770 for more details.
# KERNEL:
# KERNEL: (Specify +UVM_NO_RELNOTES to turn off this notice)
# KERNEL:
# KERNEL: ASDB file was created in location /home/runner/dataset.asdb
run -all;
# KERNEL: UVM_INFO @ 0: reporter [RNTST] Running test ...
# KERNEL: UVM_INFO /home/runner/testbench.sv(16) @ 0: env [LABEL] Started connect phase.
# KERNEL: UVM_INFO /home/runner/testbench.sv(20) @ 0: env [LABEL] Finished connect phase.
# KERNEL: UVM_INFO /home/runner/testbench.sv(25) @ 0: env [LABEL] Started run phase.
# KERNEL: UVM_INFO /home/runner/testbench.sv(34) @ 250: env [RESULT] 2 + 3 = 5
# KERNEL: UVM_INFO /home/runner/testbench.sv(36) @ 250: env [LABEL] Finished run phase.
# KERNEL: UVM_INFO /home/build/vlib1/vlib/uvm-1.2/src/base/uvm_objection.svh(1271) @ 250: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
# KERNEL: UVM_INFO /home/build/vlib1/vlib/uvm-1.2/src/base/uvm_report_server.svh(862) @ 250: reporter [UVM/REPORT/SERVER]
# KERNEL: --- UVM Report Summary ---
# KERNEL:
# KERNEL: ** Report counts by severity
# KERNEL: UVM_INFO : 8
# KERNEL: UVM_WARNING : 0
# KERNEL: UVM_ERROR : 0
# KERNEL: UVM_FATAL : 0
# KERNEL: ** Report counts by id
# KERNEL: [LABEL] 4
# KERNEL: [RESULT] 1
# KERNEL: [RNTST] 1
# KERNEL: [TEST_DONE] 1
# KERNEL: [UVM/RELNOTES] 1
# KERNEL:
# RUNTIME: Info: RUNTIME_0068 uvm_root.svh (521): $finish called.
# KERNEL: Time: 250 ns, Iteration: 57, Instance: /top, Process: @INITIAL#51_0@.
# KERNEL: stopped at time: 250 ns
# VSIM: Simulation has finished. There are no more test vectors to simulate.
exit
# VSIM: Simulation has finished.
Done

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