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SV/Verilog Testbench
SV/Verilog Design
Results
[2014-06-28 20:26:53 UTC] vlib work && vlog -writetoplevels modelsim.tops '-timescale' '1ns/1ns' '-mfcu' '+acc=rmb' '-sv' +incdir+$UVM_HOME/src $UVM_HOME/src/uvm.sv design.sv testbench.sv && c99 -fPIC -DQUESTA -g -W -shared -x c -I$MTI_HOME/include $UVM_HOME/src/dpi/uvm_dpi.cc -o uvm_dpi.so -m32 && vsim -c -do "onElabError resume; run -all; exit" -f modelsim.tops -sv_lib uvm_dpi '+UVM_VERBOSITY=UVM_HIGH' '-suppress' '3829'
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling package uvm_pkg
** Warning: /playground_lib/uvm-1.2/src/base/uvm_event.svh(40): (vlog-2181) Use of a parameterized class uvm_event_callback as a type creates a default specialization.
** Warning: /playground_lib/uvm-1.2/src/seq/uvm_sequencer_base.svh(1499): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
** Warning: /playground_lib/uvm-1.2/src/seq/uvm_sequencer_base.svh(1662): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
** Warning: /playground_lib/uvm-1.2/src/seq/uvm_sequence_base.svh(1333): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
-- Compiling module ADD_SUB
-- Compiling interface add_sub_if
-- Compiling package uvm_sv_unit
-- Importing package uvm_pkg
** Warning: /playground_lib/uvm-1.2/src/base/uvm_event.svh(40): (vlog-2181) Use of a parameterized class uvm_event_callback as a type creates a default specialization.
-- Compiling module top

Top level modules:
top
** Warning: (vlog-2650) 'bind' found in compilation unit scope. Please use -cuname to ensure that 'bind' gets elaborated.
In file included from /playground_lib/uvm-1.2/src/dpi/uvm_dpi.cc:35:
/playground_lib/uvm-1.2/src/dpi/uvm_common.c:29: warning: 'static' is not at beginning of declaration
Reading /altera-quartus/13.1/modelsim_ase/tcl/vsim/pref.tcl

# 10.1d

# vsim +UVM_VERBOSITY=UVM_HIGH -do {onElabError resume; run -all; exit} -c -suppress 3829 -sv_lib uvm_dpi top
# Loading /var/tmp/unknown@7de208125f1e_dpi_50/linuxpe_gcc-4.5.0/export_tramp.so
# Loading sv_std.std
# Loading work.uvm_pkg
# Loading work.uvm_sv_unit
# ** Note: (vsim-8785) UVM-aware debugging capabilities will be disabled since no compiled "questa_uvm_pkg" can be found.
# This also means that later if you turn on UVM-aware debugging your debug simulations may have
# different random seeds from your non-debug simulations.
# Loading work.top
# Loading work.ADD_SUB
# Loading work.add_sub_if
# ** Warning: (vsim-3017) testbench.sv(49): [TFMPC] - Too few port connections. Expected 5, found 1.
# Region: /top/dut
# ** Warning: (vsim-3722) testbench.sv(49): [TFMPC] - Missing connection for port 'a0'.
# ** Warning: (vsim-3722) testbench.sv(49): [TFMPC] - Missing connection for port 'b0'.
# ** Warning: (vsim-3722) testbench.sv(49): [TFMPC] - Missing connection for port 'doAdd0'.
# ** Warning: (vsim-3722) testbench.sv(49): [TFMPC] - Missing connection for port 'result0'.
# Compiling /var/tmp/unknown@7de208125f1e_dpi_50/linuxpe_gcc-4.5.0/exportwrapper.c
# Loading /var/tmp/unknown@7de208125f1e_dpi_50/linuxpe_gcc-4.5.0/dpi_auto_compile.so
# Loading ./uvm_dpi.so
# ** Warning: Design size of 5 instances exceeds ModelSim ALTERA recommended capacity.
# This may because you are loading cell libraries which are not recommended with
# the ModelSim Altera version. Expect performance to be adversely affected.
# onElabError resume
# resume
# run -all
# UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_root.svh(392) @ 0: reporter [UVM/RELNOTES]
# ----------------------------------------------------------------
# UVM-1.2
# (C) 2007-2014 Mentor Graphics Corporation
# (C) 2007-2014 Cadence Design Systems, Inc.
# (C) 2006-2014 Synopsys, Inc.
# (C) 2011-2013 Cypress Semiconductor Corp.
# (C) 2013-2014 NVIDIA Corporation
# ----------------------------------------------------------------
#
# *********** IMPORTANT RELEASE NOTES ************
#
# You are using a version of the UVM library that has been compiled
# with `UVM_NO_DEPRECATED undefined.
# See http://www.eda.org/svdb/view.php?id=3313 for more details.
#
# You are using a version of the UVM library that has been compiled
# with `UVM_OBJECT_DO_NOT_NEED_CONSTRUCTOR undefined.
# See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
# (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO @ 0: reporter [RNTST] Running test ...
# UVM_INFO testbench.sv(16) @ 0: env [LABEL] Started connect phase.
# UVM_INFO testbench.sv(20) @ 0: env [LABEL] Finished connect phase.
# UVM_INFO testbench.sv(25) @ 0: env [LABEL] Started run phase.
# UVM_INFO testbench.sv(34) @ 250: env [RESULT] 2 + 3 = 5
# UVM_INFO testbench.sv(36) @ 250: env [LABEL] Finished run phase.
# UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_objection.svh(1271) @ 250: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
# UVM_INFO /playground_lib/uvm-1.2/src/base/uvm_report_server.svh(847) @ 250: reporter [UVM/REPORT/SERVER]
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 8
# UVM_WARNING : 0
# UVM_ERROR : 0
# UVM_FATAL : 0
# ** Report counts by id
# [LABEL] 4
# [RESULT] 1
# [RNTST] 1
# [TEST_DONE] 1
# [UVM/RELNOTES] 1
#
# ** Note: $finish : /playground_lib/uvm-1.2/src/base/uvm_root.svh(517)
# Time: 250 ns Iteration: 70 Instance: /top
Done

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