Languages & Libraries

  Testbench + Design
  UVM / OVM  
  Other Libraries  
  Top entity
  Top class  

 Tools & Simulators

  Compile & Run Options
  Compile & Run Options
  Compile & Run Options   Run Time:
  Compile & Run Options   Run Time:
  Compile & Run Options   Run Time:
  Compile & Run Options   Run Time:
  Compile Options
  Compile & Run Options
  Compile & Run Options
  Compile & Run Options
  Compile & Run Options
  Compile & Run Options



 Easier UVM
 e + Verilog
 Python + Verilog
 Python only

SV/Verilog Testbench
SV/Verilog Design
[2014-08-09 18:19:25 EDT] $SVUNIT_INSTALL/bin/create_testsuite.pl -add ./testbench.sv -out _testsuite.sv && $SVUNIT_INSTALL/bin/create_testrunner.pl -add ./_testsuite.sv -out _testrunner.sv && vlib work && vlog '-timescale' '1ns/1ns' '-sv2k9' +define+SVUNIT_VERSION='"SVUnit v2.11"' +incdir+$SVUNIT_INSTALL/svunit_base +incdir+$SVUNIT_INSTALL/svunit_base/uvm-mock $SVUNIT_INSTALL/svunit_base/svunit_pkg.sv design.sv testbench.sv _testsuite.sv _testrunner.sv && vsim -c -do "vsim +access+r; run -all; exit"

SVUNIT: Output File: _testsuite.sv

SVUNIT: Creating class _testsuite:

SVUNIT: Creating instances for:

SVUNIT: Output File: _testrunner.sv

SVUNIT: Creating testrunner _testrunner:

SVUNIT: Creating instances for:

VSIMSA: Configuration file changed: `/home/runner/library.cfg'
ALIB: Library `work' attached.
work = /home/runner/work/work.lib
MESSAGE "Pass 1. Scanning modules hierarchy."
MESSAGE "Pass 2. Processing instantiations."
WARNING VCP2597 "Some unconnected ports remain at instance: uut. Module svunitOnSwitch has unconnected port(s) : on." "testbench.sv" 147 1
MESSAGE "Pass 3. Processing behavioral statements."
WARNING VCP2814 "Function true should return a value." "design.sv" 13 23
WARNING VCP2814 "Function false should return a value." "design.sv" 17 24
WARNING VCP2814 "Function return43 should return a value." "design.sv" 21 25
MESSAGE "Running Optimizer."
MESSAGE "ELB/DAG code generating."
MESSAGE "Unit top modules: _testrunner."
MESSAGE "$root top modules: _testrunner."
SUCCESS "Compile success 0 Errors 4 Warnings Analysis time: 0[s]."
ALOG: Warning: The source is compiled without the -dbg switch. Line breakpoints and assertion debug will not be available.
# Aldec, Inc. Riviera-PRO version 2014.06.88.5387 built for Linux64 on June 25, 2014.
# HDL, SystemC, and Assertions simulator, debugger, and design environment.
# (c) 1999-2014 Aldec, Inc. All rights reserved.
vsim +access+r;
# ELBREAD: Elaboration process.
# ELBREAD: Elaboration time 0.0 [s].
# KERNEL: Main thread initiated.
# KERNEL: Kernel process initialization phase.
# KERNEL: Time resolution set to 1ns.
# ELAB2: Elaboration final pass...
# ELAB2: Create instances ...
# ELBREAD: Warning: Too few port connections. Region: /_testrunner/_ts/svunitDemo_ut/uut
# ELAB2: Create instances complete.
# SLP: Started
# SLP: Elaboration phase ...
# SLP: Elaboration phase ... done : 0.1 [s]
# SLP: Generation phase ...
# SLP: Generation phase ... done : 0.1 [s]
# SLP: Finished : 0.1 [s]
# SLP: 0 primitives and 1 (50.00%) other processes in SLP
# SLP: 0 signals in SLP and 1 (0.21%) interface signals
# ELAB2: Elaboration final pass complete - time: 0.2 [s].
# KERNEL: SLP loading done - time: 0.0 [s].
# KERNEL: Warning: You are using the Riviera-PRO EDU Edition. The performance of simulation is reduced.
# KERNEL: Warning: Contact Aldec for available upgrade options - sales@aldec.com.
# KERNEL: SLP simulation initialization done - time: 0.0 [s].
# KERNEL: Kernel process initialization done.
# Allocation: Simulator allocated 5618 kB (elbread=1032 elab2=4403 kernel=182 sdf=0)
# KERNEL: ASDB file was created in location /home/runner/dataset.asdb
run -all;
# KERNEL: INFO: [0][_ts]: Registering Unit Test Case svunitDemo_ut
# KERNEL: INFO: [0][_testrunner]: Registering Test Suite _ts
# KERNEL: INFO: [0][svunitDemo_ut]: RUNNING
# KERNEL: INFO: [0][svunitDemo_ut]: true_returns_1::RUNNING
# KERNEL: ERROR: [0][svunitDemo_ut]: fail_unless: uut.true() === 1 (at /home/runner/testbench.sv line:73)
# KERNEL: INFO: [0][svunitDemo_ut]: true_returns_1::FAILED
# KERNEL: INFO: [0][svunitDemo_ut]: false_returns_0::RUNNING
# KERNEL: ERROR: [0][svunitDemo_ut]: fail_unless: uut.false() === 0 (at /home/runner/testbench.sv line:83)
# KERNEL: INFO: [0][svunitDemo_ut]: false_returns_0::FAILED
# KERNEL: INFO: [0][svunitDemo_ut]: return43::RUNNING
# KERNEL: ERROR: [0][svunitDemo_ut]: fail_unless: uut.return43() === 43 (at /home/runner/testbench.sv line:94)
# KERNEL: INFO: [0][svunitDemo_ut]: return43::FAILED
# KERNEL: INFO: [0][svunitDemo_ut]: turn_on::RUNNING
# KERNEL: ERROR: [0][svunitDemo_ut]: fail_unless: uut.on === 1 (at /home/runner/testbench.sv line:106)
# KERNEL: INFO: [0][svunitDemo_ut]: turn_on::FAILED
# KERNEL: INFO: [0][svunitDemo_ut]: turn_off::RUNNING
# KERNEL: ERROR: [0][svunitDemo_ut]: fail_unless: uut.on === 0 (at /home/runner/testbench.sv line:117)
# KERNEL: INFO: [0][svunitDemo_ut]: turn_off::FAILED
# KERNEL: INFO: [0][svunitDemo_ut]: FAILED (0 of 5 tests passing)
# KERNEL: INFO: [0][_ts]: FAILED (0 of 1 testcases passing)
# KERNEL: INFO: [0][_testrunner]: FAILED (0 of 1 suites passing) [SVUnit v2.11]
# RUNTIME: Info: RUNTIME_0068 _testrunner.sv (40): $finish called.
# KERNEL: Time: 0 ns, Iteration: 0, Instance: /_testrunner, Process: @INITIAL#26_0@.
# KERNEL: stopped at time: 0 ns
# VSIM: Simulation has finished. There are no more test vectors to simulate.
# VSIM: Simulation has finished.


Upload files...

(drag and drop anywhere)


Upload files...

(drag and drop anywhere)

Please confirm to remove:
Please confirm to remove: