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SV/Verilog Testbench
SV/Verilog Design
[2013-12-13 16:16:56 UTC] $SVUNIT_INSTALL/bin/create_testsuite.pl -add ./testbench -out testsuite.sv && $SVUNIT_INSTALL/bin/create_testrunner.pl -add ./testsuite.sv -out testrunner.sv && vlib work && vlog -writetoplevels modelsim.tops '-timescale' '1ns/1ns' '-mfcu' '+acc=rmb' '-sv' +define+SVUNIT_VERSION='"SVUnit v2.5"' +incdir+$SVUNIT_INSTALL/svunit_base +incdir+$SVUNIT_INSTALL/svunit_base/uvm-mock $SVUNIT_INSTALL/svunit_base/svunit_pkg.sv design testbench testsuite.sv testrunner.sv && vsim -c -do "onElabError resume; run -all; exit" -f modelsim.tops

SVUNIT: Output File: testsuite.sv

SVUNIT: Creating class testsuite:

SVUNIT: Creating instances for:

SVUNIT: Output File: testrunner.sv

SVUNIT: Creating testrunner testrunner:

SVUNIT: Creating instances for:

Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling package svunit_pkg
-- Compiling interface svunitOnSwitch
** Warning: design(13): (vlog-2250) Function "true" has no return value assignment.
** Warning: design(17): (vlog-2250) Function "false" has no return value assignment.
** Warning: design(21): (vlog-2250) Function "return43" has no return value assignment.
-- Compiling package svunit_pkg_sv_unit
-- Importing package svunit_pkg
-- Compiling module svunitDemo_unit_test
-- Compiling module testsuite
-- Compiling module testrunner

Top level modules:
Reading /altera-quartus/13.1/modelsim_ase/tcl/vsim/pref.tcl

# 10.1d

# vsim -do {onElabError resume; run -all; exit} -c testrunner
# Loading sv_std.std
# Loading work.svunit_pkg
# Loading work.svunit_pkg_sv_unit
# Loading work.testrunner
# Loading work.testsuite
# Loading work.svunitDemo_unit_test
# Loading work.svunitOnSwitch
# ** Warning: (vsim-3017) testbench(147): [TFMPC] - Too few port connections. Expected 1, found 0.
# Region: /testrunner/testsuite/svunitDemo_ut/uut
# ** Warning: (vsim-3722) testbench(147): [TFMPC] - Missing connection for port 'on'.
# onElabError resume
# resume
# run -all
# INFO: [0][testsuite]: Registering Unit Test Case svunitDemo_ut
# INFO: [0][testrunner]: Registering Test Suite testsuite
# INFO: [0][testsuite]: RUNNING
# INFO: [0][svunitDemo_ut]: RUNNING
# INFO: [0][svunitDemo_ut]: true_returns_1::RUNNING
# ERROR: [0][svunitDemo_ut]: fail_unless: uut.true() === 1 (at testbench line:73)
# INFO: [0][svunitDemo_ut]: true_returns_1::FAILED
# INFO: [0][svunitDemo_ut]: false_returns_0::RUNNING
# ERROR: [0][svunitDemo_ut]: fail_unless: uut.false() === 0 (at testbench line:83)
# INFO: [0][svunitDemo_ut]: false_returns_0::FAILED
# INFO: [0][svunitDemo_ut]: return43::RUNNING
# ERROR: [0][svunitDemo_ut]: fail_unless: uut.return43() === 43 (at testbench line:94)
# INFO: [0][svunitDemo_ut]: return43::FAILED
# INFO: [0][svunitDemo_ut]: turn_on::RUNNING
# ERROR: [0][svunitDemo_ut]: fail_unless: uut.on === 1 (at testbench line:106)
# INFO: [0][svunitDemo_ut]: turn_on::FAILED
# INFO: [0][svunitDemo_ut]: turn_off::RUNNING
# ERROR: [0][svunitDemo_ut]: fail_unless: uut.on === 0 (at testbench line:117)
# INFO: [0][svunitDemo_ut]: turn_off::FAILED
# INFO: [0][svunitDemo_ut]: FAILED (0 of 5 tests passing)
# INFO: [0][testsuite]: FAILED (0 of 1 testcases passing)
# INFO: [0][testrunner]: FAILED (0 of 1 suites passing) [SVUnit v2.5]


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