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SV/Verilog Testbench
SV/Verilog Design
Results
[2014-01-17 14:07:33 UTC] vlib work && vlog -writetoplevels modelsim.tops '-timescale' '1ns/1ns' '-mfcu' '+acc=rmb' '-sv' +incdir+$UVM_HOME/src $UVM_HOME/src/uvm.sv design.sv testbench.sv && c99 -m32 -fPIC -DQUESTA -g -W -shared -x c -I$MTI_HOME/include $UVM_HOME/src/dpi/uvm_dpi.cc -o uvm_dpi.so && vsim -c -do "onElabError resume; run -all; exit" -f modelsim.tops -sv_lib uvm_dpi '-suppress' '3829'
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling package uvm_pkg
** Warning: /playground_lib/uvm-1.1d/src/seq/uvm_sequencer_base.svh(1398): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
** Warning: /playground_lib/uvm-1.1d/src/seq/uvm_sequencer_base.svh(1539): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
** Warning: /playground_lib/uvm-1.1d/src/seq/uvm_sequence_base.svh(1105): (vlog-2186) SystemVerilog testbench feature
(randomization, coverage or assertion) detected in the design.
These features are only supported in Questasim.
-- Compiling interface adpcm_if
-- Compiling package adpcm_pkg
-- Importing package uvm_pkg
-- Compiling module top_tb
-- Importing package adpcm_pkg

Top level modules:
top_tb
Reading /altera-quartus/13.1/modelsim_ase/tcl/vsim/pref.tcl

# 10.1d

# vsim -do {onElabError resume; run -all; exit} -c -suppress 3829 -sv_lib uvm_dpi top_tb
# Loading sv_std.std
# Loading work.uvm_pkg
# Loading work.adpcm_pkg
# ** Note: (vsim-8785) UVM-aware debugging capabilities will be disabled since no compiled "questa_uvm_pkg" can be found.
# This also means that later if you turn on UVM-aware debugging your debug simulations may have
# different random seeds from your non-debug simulations.
# Loading work.top_tb
# Loading work.adpcm_if
# Loading ./uvm_dpi.so
# ** Warning: Design size of 4 instances exceeds ModelSim ALTERA recommended capacity.
# This may because you are loading cell libraries which are not recommended with
# the ModelSim Altera version. Expect performance to be adversely affected.
# onElabError resume
# resume
# run -all
# ----------------------------------------------------------------
# UVM-1.1d
# (C) 2007-2013 Mentor Graphics Corporation
# (C) 2007-2013 Cadence Design Systems, Inc.
# (C) 2006-2013 Synopsys, Inc.
# (C) 2011-2013 Cypress Semiconductor Corp.
# ----------------------------------------------------------------
#
# *********** IMPORTANT RELEASE NOTES ************
#
# You are using a version of the UVM library that has been compiled
# with `UVM_NO_DEPRECATED undefined.
# See http://www.eda.org/svdb/view.php?id=3313 for more details.
#
# You are using a version of the UVM library that has been compiled
# with `UVM_OBJECT_MUST_HAVE_CONSTRUCTOR undefined.
# See http://www.eda.org/svdb/view.php?id=3770 for more details.
#
# (Specify +UVM_NO_RELNOTES to turn off this notice)
#
# UVM_INFO @ 0: reporter [RNTST] Running test adpcm_test...
# UVM_INFO testbench.sv(150) @ 170: uvm_test_top.m_sequencer@@test_seq [ADPCM_TX_SEQ_BODY] Transmitted frame 0
# UVM_INFO testbench.sv(150) @ 470: uvm_test_top.m_sequencer@@test_seq [ADPCM_TX_SEQ_BODY] Transmitted frame 1
# UVM_INFO testbench.sv(150) @ 750: uvm_test_top.m_sequencer@@test_seq [ADPCM_TX_SEQ_BODY] Transmitted frame 2
# UVM_INFO testbench.sv(150) @ 1050: uvm_test_top.m_sequencer@@test_seq [ADPCM_TX_SEQ_BODY] Transmitted frame 3
# UVM_INFO testbench.sv(150) @ 1510: uvm_test_top.m_sequencer@@test_seq [ADPCM_TX_SEQ_BODY] Transmitted frame 4
# UVM_INFO testbench.sv(150) @ 1690: uvm_test_top.m_sequencer@@test_seq [ADPCM_TX_SEQ_BODY] Transmitted frame 5
# UVM_INFO testbench.sv(150) @ 2110: uvm_test_top.m_sequencer@@test_seq [ADPCM_TX_SEQ_BODY] Transmitted frame 6
# UVM_INFO testbench.sv(150) @ 2290: uvm_test_top.m_sequencer@@test_seq [ADPCM_TX_SEQ_BODY] Transmitted frame 7
# UVM_INFO testbench.sv(150) @ 2490: uvm_test_top.m_sequencer@@test_seq [ADPCM_TX_SEQ_BODY] Transmitted frame 8
# UVM_INFO testbench.sv(150) @ 2750: uvm_test_top.m_sequencer@@test_seq [ADPCM_TX_SEQ_BODY] Transmitted frame 9
# UVM_INFO /playground_lib/uvm-1.1d/src/base/uvm_objection.svh(1268) @ 2750: reporter [TEST_DONE] 'run' phase is ready to proceed to the 'extract' phase
#
# --- UVM Report Summary ---
#
# ** Report counts by severity
# UVM_INFO : 12
# UVM_WARNING : 0
# UVM_ERROR : 0
# UVM_FATAL : 0
# ** Report counts by id
# [ADPCM_TX_SEQ_BODY] 10
# [RNTST] 1
# [TEST_DONE] 1
# ** Note: $finish : /playground_lib/uvm-1.1d/src/base/uvm_root.svh(430)
# Time: 2750 ns Iteration: 61 Instance: /top_tb
Done

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