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SV/Verilog Testbench
SV/Verilog Design
Results
[2014-03-20 03:14:15 UTC] vlib work && vlog -writetoplevels modelsim.tops '-timescale' '1ns/1ns' '-mfcu' '+acc=rmb' '-sv' '-suppress' '2181' design.sv testbench.sv && vsim -c -do "onElabError resume; run -all; exit" -f modelsim.tops '-suppress' '3829'
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module par4
-- Compiling module test

Top level modules:
test
Reading /altera-quartus/13.1/modelsim_ase/tcl/vsim/pref.tcl

# 10.1d

# vsim -do {onElabError resume; run -all; exit} -c -suppress 3829 test
# Loading sv_std.std
# Loading work.test
# Loading work.par4
# onElabError resume
# resume
# run -all
# ** Note: $finish : testbench.sv(11)
# Time: 25 ns Iteration: 0 Instance: /test
Finding VCD file...
./dump.vcd
[2014-03-20 03:14:16 UTC] Opening EPWave...
Done

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