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SV/Verilog Testbench
SV/Verilog Design
Results
[2014-04-06 15:00:45 UTC] vlib work && vlog -writetoplevels modelsim.tops '-timescale' '1ns/1ns' '-mfcu' '+acc=rmb' '-sv' '-suppress' '2181' design.sv testbench.sv && vsim -c -do "onElabError resume; run -all; exit" -f modelsim.tops '-suppress' '3829'
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module counter5
-- Compiling module test

Top level modules:
counter5
test
Reading /altera-quartus/13.1/modelsim_ase/tcl/vsim/pref.tcl

# 10.1d

# vsim -do {onElabError resume; run -all; exit} -c -suppress 3829 counter5 test
# Loading sv_std.std
# Loading work.counter5
# Loading work.test
# ** Error: (vsim-3033) testbench.sv(20): Instantiation of 'pcounter5' failed. The design unit was not found.
# Region: /test
# Searched libraries:
# /home/runner/work
# Error loading design
Error loading design
Exit code expected: 0, received: 255
Done

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