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SV/Verilog Testbench
SV/Verilog Design
Results
[2014-04-05 17:20:54 UTC] vlib work && vlog -writetoplevels modelsim.tops '-timescale' '100s/1ns' '-mfcu' '+acc=rmb' '-sv' '-suppress' '2181' design.sv testbench.sv && vsim -c -do "onElabError resume; run -all; exit" -f modelsim.tops '-suppress' '3829'
Model Technology ModelSim ALTERA vlog 10.1d Compiler 2012.11 Nov 2 2012
-- Compiling module test
-- Compiling module testtb

Top level modules:
testtb
Reading /altera-quartus/13.1/modelsim_ase/tcl/vsim/pref.tcl

# 10.1d

# vsim -do {onElabError resume; run -all; exit} -c -suppress 3829 testtb
# Loading sv_std.std
# Loading work.testtb
# Loading work.test
# onElabError resume
# resume
# run -all
# ** Note: $finish : testbench.sv(24)
# Time: 9300 sec Iteration: 0 Instance: /testtb
Finding VCD file...
./test.vcd
[2014-04-05 17:20:55 UTC] Opening EPWave...
Done

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