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Language
VHDL
SystemVerilog/Verilog
Specman e + SV/Verilog
Python + SV/Verilog
Python only
C++/SystemC
Perl
Csh
Simulator
GHDL 0.35
Csh
C++
Synopsys VCS 2014.10
VTR 7.0
Yosys 0.2.0
Aldec Riviera Pro 2017.02
Aldec Riviera Pro 2015.06
VeriWell 2.8.7
Cadence Incisive 15.20
Icarus Verilog 0.10.0 11/23/14
Aldec Riviera Pro 2014.10
Aldec Riviera Pro 2014.06
Python
GPL Cver 2.12.a
Icarus Verilog 0.9.7
Icarus Verilog 0.9.6
Yosys 0.3.0
Perl
Methodology
UVM
OVM
cocotb
MyHDL
Migen
OSVVM
UVVM
OVL
Easier UVM
Examples only
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